Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

Design of ultra high-speed CMOS CML buffers and latches

A comprehensive study of ultra high-speed current-mode logic (CML) buffers and regenerative CML latches will be illustrated. A new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, a new 20GHz regenerative latch circuit will be introduced. Experimental results show a higher performance for the new latch architecture compared to a conventional CML latch ...

Complementary high-speed SiGe and CMOS buffers

A Negative Conductance Voltage Gain Enhancement Technique for Low Voltage High Speed CMOS Op Amp Design

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the out...

Design and Analysis of Low-Voltage Current-Mode Logic Buffers

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design ...

DESIGN OF HIGH SPEED LOW VOLTAGE COMPARATOR DESIGN ON 180nm CMOS

In this paper, A CMOS comparator with high low power application is presented. The comparator has been designed and simulated in 180nm CMOS technology. It is designed to sense low voltage using Double-Tail Dual-Rail Dynamic switching method.